CMOS工艺基本流程

CMOSCMOS工艺工艺 1 CMOS 全称全称Complementary Metal Oxide Semiconductor 即互补金属氧化物半导体是一种即互补金属氧化物半导体是一种大规模应用于集成电路芯片制造的原料采用大规模应用于集成电路芯片制造的原料采用CMOS 技术可以将成对的金属氧化物半导体场效应晶体管技术可以将成对的金属氧化物半导体场效应晶体管 MOSFET 集成在一块硅片上集成在一块硅片上 2 Silicon Substrate P 2um 725um Silicon Epi Layer P 选择衬底选择衬底基础基础晶圆的选择掺杂类型 N或P 电阻率掺杂浓度晶向高掺杂 P 的Si晶圆低掺杂 P 的Si外延层 3 Silicon Substrate P Silicon Epi Layer P Pad Oxide 热氧化热氧化形成一个SiO2薄层厚度约20nm 高温 H2O或O2气氛缓解后续步骤形成的Si3N4对Si衬底造成的应力 4 Silicon Substrate P Silicon Epi Layer P Silicon Nitride Si3N4淀积 Si3N4淀积厚度约250nm 化学气相淀积 CVD 作为后续CMP的停止层 5 Silicon Substrate P Silicon Epi Layer P Silicon Nitride Photoresist 光刻胶成形光刻胶成形厚度约0 5 1 0um 光刻胶涂敷曝光和显影用于隔离浅槽的定义 6 Silicon Substrate P Silicon Epi Layer P Silicon Nitride Photoresist Si3N4和SiO2刻蚀 Si3N4和SiO2刻蚀基于氟的反应离子刻蚀 RIE 7 Silicon Substrate P Silicon Epi Layer P Silicon Nitride Photoresist Transistor Active Areas Isolation Trenches 隔离浅槽刻蚀隔离浅槽刻蚀基于氟的反应离子刻蚀 RIE 定义晶体管有源区 8 Silicon Substrate P Silicon Epi Layer P Silicon Nitride Transistor Active Areas Isolation Trenches 除去光刻胶除去光刻胶氧等离子体去胶把光刻胶成分氧化为气体 9 Silicon Substrate P Silicon Epi Layer P Silicon Nitride Future PMOS Transistor Silicon Dioxide Future NMOS Transistor No current can flow through here SiO2淀积 SiO2淀积用氧化物填充隔离浅槽厚度约为0 5 1 0um 和浅槽深度和几何形状有关化学气相淀积 CVD 10 Silicon Substrate P Silicon Epi Layer P Silicon Nitride Future PMOS Transistor Future NMOS Transistor No current can flow through here 化学机械抛光化学机械抛光 CMP CMP除去表面的氧化层到Si3N4层为止 11 Silicon Substrate P Silicon Epi Layer P Future PMOS Transistor Future NMOS Transistor 除去Si3N4 除去Si3N4 热磷酸 H3PO4 湿法刻蚀约180 12 Trench Oxide Cross Section Bare Silicon 平面视图平面视图浅槽隔离浅槽隔离完成浅槽隔离 STI 13 Silicon Substrate P Silicon Epi Layer P Future PMOS Transistor Future NMOS Transistor Photoresist 光刻胶成形光刻胶成形厚度比较厚用于阻挡离子注入用于N 阱的定义 14 Silicon Substrate P Silicon Epi Layer P Future NMOS Transistor Photoresist N Well Phosphorous Ions 磷离子注入磷离子注入高能磷离子注入形成局部N型区域用于制造PMOS管 15 Silicon Substrate P Silicon Epi Layer P Future NMOS Transistor N Well 除去光刻胶 16 Photoresist Silicon Substrate P Silicon Epi Layer P Future NMOS Transistor N Well 光刻胶成形光刻胶成形厚度比较厚用于阻挡离子注入用于P 阱的定义 17 Silicon Substrate P Silicon Epi Layer P Photoresist N Well Boron Ions P Well 硼离子注入高能硼离子注入形成局部P型区域用于制造NMOS管硼离子注入 18 Silicon Substrate P Silicon Epi Layer P N Well P Well 除去光刻胶 19 Silicon Substrate P Silicon Epi Layer P P Well N Well 退火退火在600 1000 的H2环境中加热修复离子注入造成的Si表面晶体损伤注入杂质的电激活同时会造成杂质的进一步扩散快速加热工艺 RTP 可以减少杂质的扩散 20 Trench Oxide N Well P Well Cross Section 完成N 阱和P 阱平面平面视图视图 NN阱与阱与P P阱阱 21 Silicon Substrate P Silicon Epi Layer P P Well N Well Sacrificial Oxide 牺牲氧化层生长牺牲氧化层生长牺牲氧化层生长厚度约25nm 用来捕获Si表面的缺陷 22 Silicon Substrate P Silicon Epi Layer P P Well N Well 除去牺牲氧化层除去牺牲氧化层 HF溶液湿法刻蚀剩下洁净的Si表面 23 Silicon Substrate P Silicon Epi Layer P P Well N Well Gate Oxide 栅氧化层生长栅氧化层生长工艺中最关键的一步厚度2 10nm 要求非常洁净厚度精确 1 用作晶体管的栅绝缘层 24 Silicon Substrate P Silicon Epi Layer P P Well N Well Polysilicon 多晶硅淀积多晶硅淀积厚度150 300nm 化学气相淀积 CVD 25 Silicon Substrate P Silicon Epi Layer P P Well N Well Photoresist Channel Length Polysilicon 光刻胶成形光刻胶成形工艺中最关键的图形转移步骤栅长的精确性是晶体管开关速度的首要决定因素使用最先进的曝光技术深紫外光 DUV 光刻胶厚度比其他步骤薄 26 Silicon Substrate P Silicon Epi Layer P P Well N Well Photoresist Channel Length 多晶硅刻蚀多晶硅刻蚀基于氟的反应离子刻蚀 RIE 必须精确的从光刻胶得到多晶硅的形状 27 Silicon Substrate P Silicon Epi Layer P P Well N Well Gate Oxide Poly Gate Electrode 除去光刻胶 28 Trench Oxide N Well P Well Cross Section Polysilicon 平面平面视图视图栅极栅极完成栅极 29 Silicon Substrate P Silicon Epi Layer P P Well N Well Gate Oxide Poly Gate Electrode Poly Re oxidation 多晶硅氧化多晶硅氧化在多晶硅表面生长薄氧化层用于缓冲隔离多晶硅和后续步骤形成的 Si3N4 30 Silicon Substrate P Silicon Epi Layer P P Well N Well Photoresist 光刻胶成形光刻胶成形用于控制NMOS管的衔接注入 31 Silicon Substrate P Silicon Epi Layer P P Well N Well Photoresist Arsenic Ions N Tip NMOS管衔接注入 NMOS管衔接注入低能量浅深度低掺杂的砷离子注入衔接注入用于削弱栅区的热载流子效应 32 Silicon Substrate P Silicon Epi Layer P P Well N Well N Tip 除去光刻胶 33 Silicon Substrate P Silicon Epi Layer P P Well N Well Photoresist N Tip 光刻胶成形光刻胶成形用于控制PMOS管的衔接注入 34 Silicon Substrate P Silicon Epi Layer P P Well N Well Photoresist BF2 Ions N Tip P Tip PMOS管衔接注入低能量浅深度低掺杂的BF2 离子注入衔接注入用于削弱栅区的热载流子效应 PMOS管衔接注入 35 Silicon Substrate P Silicon Epi Layer P P Well N Well N Tip P Tip 除去光刻胶 36 Silicon Substrate P Silicon Epi Layer P P Well N Well Silicon Nitride Thinner Here Thicker Here N Tip P Tip P Tip Si3N4淀积 Si3N4淀积厚度120 180nm CVD 37 Silicon Substrate P Silicon Epi Layer P P Well N Well Spacer Sidewall N Tip P Tip P Tip Si3N4刻蚀 Si3N4刻蚀水平表面的薄层Si3N4被刻蚀留下隔离侧墙侧墙精确定位晶体管源区和漏区的离子注入 RIE 38 Silicon Substrate P Silicon Epi Layer P P Well N Well Photoresist N Tip P Tip 光刻胶成形光刻胶成形用于控制NMOS管的源漏区注入 39 Silicon Substrate P Silicon Epi Layer P P Well N Well Photoresist Arsenic Ions N Drain N Source P Tip NMOS管源漏注入 NMOS管源漏注入浅深度重掺杂的砷离子注入形成了重掺杂的源漏区隔离侧墙阻挡了栅区附近的注入 40 Silicon Substrate P Silicon Epi Layer P P Well N Well N Drain N Source P Tip 除去光刻胶 41 Silicon Substrate P Silicon Epi Layer P P Well N Well N Drain N Source Photoresist P Ti